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Why Use Bare Die?
Designers of space-constrained
systems face the challenge of determining how to incorporate
expanding functional needs into reduced spaces in a timely and
cost-effective manner. For many handheld, portable and other
small form factor products, silicon packaging has become the
major size-limiting element of their design layout. The
conversion from standard semiconductor packaging to unpackaged
die provides the system designer with an opportunity to make
more efficient use of limited space.
At the same time, bare die implementation affords improved
electrical performance, better signal integrity, and higher
levels of integration with reduced weight and height.
For memory the benefits of higher speeds can be realised at die
level due to the reduced path lengths and helps designers keep
up with ever increasing processor clock and bus performances. A
classic application for this is the graphics card where both
speed and integration are vital.
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Die Technology provides products that can be used in two forms
of die assemblies:
Standard bare die for wire bond applications and Bare Die bumped for
bumped flip-chip applications. Both assembly formats offer size
improvements over traditional packaged product outlines.
As shown in the figure (below), the implementation in die form
of a standard 18M Synchronous SRAM can reduce space consumption
by greater than 50%.
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Products
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Product Type |
Density |
| ASYNCHRONOUS
SRAM |
64K, 256K, 512K,
1M, 2M, 3M, 4M, 8M |
| SYNCHRONOUS SRAM |
1M, 2M, 4M,
8M,18M, 36M |
| QUAD DATA RATE
SRAM |
36M |
| DDR II SRAM |
36M |
| FPM & EDO DRAM
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4M, 16M |
| SDRAM |
16M, 64M, 128M,
256M |
| EEPROM
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1K, 2K, 4K, 8K,
16K, 32K, 64K, 128K, 256K |
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more information
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