Element Evaluations / LAT (Lot Acceptance Tests)  - The Concept

The performance of every semiconductor die is unique, although two die may derive from the same family, the same fab or even the same wafer, their electrical performance will never be 100% identical due to natural differences in atomic composition.  This performance difference is usually minute and often has no real bearing on the broader electrical template the chip designer and fabricator is aiming for.  To be sure of a products consistency an Element Evaluation/LAT can be performed.  This is usually needed when a customer requires the added assurance that their product will meet specified electrical test criteria. Often the part will need to function in extreme environments, for example when product is to be used in military applications.  Testing can cover both the mechanical and electrical reliability of the product and a LAT will determine whether or not a particular batch (diffusion lot) of semiconductor die are capable of meeting pre-defined operating limits.

Element Evaluations / LAT (Lot Acceptance Tests)  - The Process

Specification standards managed by DSCC (Defense Supply Center Columbus) are commonly referenced when a LAT is required, these can form part or all of the requirements of an LAT.  These specs are usually in the form of MIL-PRF-38534, which incorporate Class H and Class K suffix, the end user application will normally determine the type of LAT spec required.

Customer specifications can also be quoted and these can mirror a MIL spec, a manufacturers datasheet or call for testing outside of the manufacturers guaranteed design parameters.  Our team of engineers at Die Technology can advise and offer consultancy prior to work being undertaken where we feel that a specification may not be met by the devices being tested, this is a valuable resource built on years of experience and can often save time and money.  When necessary we can assist in defining specifications that meet your applications requirements.

Element Evaluations / LAT (Lot Acceptance Tests)  - Capabilities

Die Technology Ltd has the expertise and capability to test a wide range of semiconductor devices.  Our knowledge of both product and end user applications allow us to offer an extensive portfolio of electrical testing.

Product can be tested over temperature ranges of +25^OC to +125^OC for die/wafer and –70^OC to +200^OC for packaged devices.

LAT/Element Evaluations can be tested to conform to manufacturers published datasheets or customer defined specifications, together with industry standards incorporating BS, CECC, MIL or SPACE level test criteria.

Each LAT order is supplied with full and comprehensive test data, together with CTR (certified test record) and packaged electrical samples.  Data can also be supplied in electronic format where requested.

Full traceability is kept on computer file indefinitely

Testing available for Product families including:

Analogue Functions

• Operational Amplifiers, Comparators, Buffers

• Diodes, Transistors (Bipolar, JFET, MOSFET types)

• Precision Voltage References, Voltage Regulators

• Analogue Switches, Multiplexers

• Analogue to Digital Converters

• Power Management IC’s, PWM, Switch Mode Controllers

• Power MOSFET’s, Power HEXFET’s

• Voltage Transient Suppressors

• Line Drivers / Receivers

• Triacs

Digital Functions

• Standard and special functions 

• 54 / 74 TTL Logic Series

• 54 / 74 CMOS Logic Series

• CD4000 CMOS Logic Series

• Line Drivers

• Decoders

• Level Translators

• Digital To Analogue Converters

• Low Voltage / Low Power CMOS

• Level Shifters / Buffers

• Decoders / Multiplexers 

Memory

• Testing of Memory devices is available on request

Mixed Signal / ASIC

• Special requirements available on request