1. The Cost Savings

Using bare die assembly to replace traditional package based assembly processes is catching on rapidly, particularly in Asia. This is most notable in high volume applications where density is required and high yield bare silicon is implemented. The lower cost of ownership takes into consideration substrate, assembly, system test, equipment utilization, rework, and increased product value. In addition, the cost of a bare die product is typically lower than the package equivalent. Process simplification - With bumped bare die and flip-chip processing, the assembly flows are streamlined by reducing the number of process steps. These bare die advantages promote higher levels of integration using existing mature products, which leads to increased functionality per square area, and reduces costs. Additionally, performance improvements are achieved with no additional cost penalty (See technical benefits). Integrating bare die for SiP (System-in-Package) solutions provides a benefit over both standard package solutions and SOC (System-on-Chip) solutions. As design cycle time requirements continue to shorten and product time to market becomes increasingly important, die for SiP solutions finds greater utility in meeting the designer's needs.

The following Matrix below offers a benchmark cost comparison of current assembly process methods in current use:

The following assumptions have been made.

1. PCB costed @ $40 per square decimetre

2. All costs based on volume of 1KK components

3. Cost model will vary slightly for higher or lower Leaded devices, the total costs per package type will still be relatively similar
   
    

Feel free to contact us and we will be happy to investigate a cost model based on your particular circumstances.

In Summary the cost benefits of using bare die assembly can be broken down as follows:

• Higher levels of integration

• Reduced Substrate size/cost

• Reduced Assembly / manufacturing process cost

• Faster Time to market

• Better Product value

• More features per bare die area & weight reduction
   

2. How to set up the bare die assembly line - key points

Firstly, if in volume, can the product be manufactured cheaper by using bare die assembly? See matrix above
Secondly are there other technical reasons to use bare die? Does it need to be smaller, lighter, dissipate more heat, or need, on certain devices, to work faster?

The Customer needs to decide on which technology is best suited for the production of the circuit. For example, for small volumes, or a wider temperature range, it is best to consider Chip on Board. For larger volumes, it is best to consider Flip Chip. There are three main options - gold stud bumps, micro posts, solder bumps and a range of die attachment methods. We at Die Technology can help you determine the most appropriate method either by correspondence or a personal visit.

It is often better to run with one option for prototypes and another for higher volumes. A product could start out as Chip on Board then, using the same equipment set, change to micropost or flip chip when the volume increases. At all stages the customer could either opt to do the work themselves, sub-contract the manufacture, or use a combination of both.

A final factor the customer needs to be aware of the upcoming Lead Free solder initiatives and how this could impact their assembly process.

To setup the assembly line Die Technology Ltd will train your company to handle bare die, inspect, assemble, and bond at any volume. Also, we can assist in the writing, or vetting, of detail specifications for bare die purchase and application notes. We have the expertise to define the whole process form start to finish and can provide full consultation and training on the equipment to needed for the application.

Your costs for this service - If we assist you by correspondence then we will not charge you, providing an agreement is made to place all the related die business with us. For off-site consultation activities, the charge is $1500 per day plus travel and expenses. These fees can also be amortised for large die orders placed with us.

3. Success Stories

Mobile phones, Lap top flexes and RFID applications are probably the best examples. Motorola's latest phone range, by using Flip Chip die, saves over fifteen percent in component costs and twenty percent of assembly costs. Sun Rise Technology in China manufacture colour screens boards for a similar spec mobile phone. The basic model used a black and white screen running off a Phillips bare die LCD Driver, which required 720 bond pads and this was attached using standard chip on board technology. The new colour version required a LCD Driver die with 940 bonds, which could not be accommodated on the periphery of the chip without significantly increasing the die size and board real-estate. By setting up a gold-flip chip assembly, we were able to place pads within the centre of the chip . This not only reduced the cost of the device but also saved Eighty Percent of the assembly time due to the chip requiring only placement on a strip of foil without need for bonding. On 30 million screens per year the saving was "Very significant!".

Other useful case studies may be found at http://www.dieproduct.com/html/apps.html

4. Technical Benefits (Provided by National Semiconductor)

Electrical Performance

The lower inductance and capacitance of bare die is important in analog, RF, and power applications. Signal propagation and

power/ground distributions are also improved.

Shorter electrical length of wirebonds and solder bumps results in lower parasitic inductance. Lower capacitance and and less distance between chips leads to improved rise times or lower strength drivers improved rise times or lower strength drivers.

Size and weight

Designers of space-constrained systems face the challenge of determining how to incorporate expanding functional needs into reduced spaces in a timely and cost-effective manner. For many handheld, portable, and other small form factor products, silicon packaging has become the major size limiting element of their design layout. The conversion from standard semiconductor packaging to unpackaged die provides the system designer with opportunities for more efficient use of limited space and also reduce height and weight.

Die products that can be used in two forms of die assemblies:
Standard bare die for wire bond applications Die for bumped flip-chip applications
Both assembly formats offer size improvements over traditional packaged product outlines.

As shown in the figure (shown below), the implementation in die form of a standard dual Phased Locked Loop can reduce space consumption by greater than 50%.

Improvements vary based on the current packaging in use; flip-chip can reduce the function footprint by 70% to 90%

Improved Integration

With reduced size and improved substrate pitch, existing product functions provide a low cost, low risk path for the designer to achieve a higher level of integration. Reduced design time is possible utilizing individual die functions in a system in a package (SiP) approach compared to developing system on a chip (SOC) product.

Reliability
The reduced number of interconnects with die use leads to improved reliability. The typical packaged part has three connection points per I/O. Compare this with only two for wire bonds and a single solder joint with flip-chip.

Typical Packaged Device Interconnects

Typical Chip on Board Interconnects

Typical Flip Chip Interconnects